The present invention relates to semiconductor devices (or semiconductor integrated circuit devices) and a cell peripheral layout technique or a breakdown voltage enhancement technique in a method for manufacturing a semiconductor device (or semiconductor integrated circuit device).
Japanese Unexamined Patent Publication No. 2007-116190 and U.S. Patent Publication 2005-098826 disclose various structures relating to layout of the vicinity of a cell region in a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a super junction structure which is manufactured by a multi-epitaxial technique or a trench insulating film filling technique (implantation of ions into trenches). These structures include P− resurf (reduced surface field) regions, ring-shaped peripheral P type drift regions based on a multi-epitaxial technique, vertically arranged linear peripheral P type drift regions based on a trench insulating film filling technique, and linear peripheral P type drift regions divided and arranged vertically/in parallel.